Open-source Verilog synthesis tool for digital circuits and open-source chip design flows.
Yosys is an open-source RTL synthesis tool that supports Verilog synthesis and many back-end outputs, and is a core component of open-source digital IC and FPGA toolchains. It suits digital circuit teaching, Verilog design verification, FPGA prototyping and front-end synthesis in open-source chip flows.
Use cases: Verilog synthesis, digital ICs, FPGA, RTL, open-source EDA, chip design teaching
Recommended combination: Yosys + nextpnr / OpenROAD / OpenLane
