Automated RTL-to-GDS flow built on open-source EDA tools, suited to open-source chip teaching and validation.
OpenLane is an automated RTL-to-GDS flow that integrates open-source tools such as OpenROAD, Yosys, Magic, KLayout and ngspice, and can be combined with open-source PDKs for digital chip design experiments. It suits open-source chip teaching, digital circuit layout generation and small chip design validation.
Use cases: open-source chips, RTL-to-GDS, digital ICs, OpenROAD flow, SkyWater PDK, chip design teaching
Note: Installation and running usually rely on a container environment; beginners are advised to start with the official example designs.
